One physical pool for Arm cores, weights, activations, and KV-cache.
Headless inference hardware
blackbox. 512 GB unified. Inference only.
A sealed node for large open language models — private on your floor, efficient by design, ready from one unit to one hundred.
davici blackbox · 220 × 220 × 105 mm · sealed monolith
DVC-1 tensor fabric
512 GB unified LPDDR
1+ TB/s memory path
350 W full inference
Design targets
More model. Less machine.
Wide LPDDR on package — the path models actually walk.
Aggregate theoretical per direction across four UALink x4 ports.
Sustained full inference budget. No graphics tax. No training tax.
Mandate
If it doesn’t emit tokens, it doesn’t ship.
Not a workstation. Not a training rack. A headless inference system — silicon, memory, and cooling aimed at language models alone.
DVC-1 architecture
One SoC. One memory pool. One job.
DVC-1 places Arm control cores, a large tensor fabric, SRAM, memory controllers, and cluster I/O on one silicon platform. CPU and accelerator share the same physical LPDDR — no shuttling between system RAM and separate VRAM.
12 Arm Neoverse-class cores for Linux, networking, tokenization, and runtime.
Tensor and matrix engines for FP4, INT4, INT8, FP8, and BF16 inference.
Distributed on-die SRAM for weight tiles, activations, attention, and KV-cache.
Fused kernels for attention, RoPE, RMSNorm, Softmax, SwiGLU, and MoE routing.
Four UALink x4 ports, PCIe 6.0 root complex, and RDMA networking.
Arm control12 cores, Linux & API
SRAM meshLocal banks near compute
Memory controllers512 GB LPDDR, ECC, 1+ TB/s
DVC-1Inference tensor fabric
SchedulersContinuous batching & paged KV
PCIe 6.0NVMe, NIC, service
4× UALink 200G x4Accelerator to accelerator
Root of trustSecure boot & signed firmware
RDMA fabric200/400G scale-out
Unified memory
512 GB where the model actually lives.
One pool.
No shuttle.
Arm cores and the inference accelerator share one physical address space. Weights, KV-cache, and runtime data live in a coherent local pool — not bounced between host memory and a separate accelerator heap.
NVMe is storage, not the working set
Active model blocks belong in LPDDR. Disk holds checkpoints and cold weights — never the hot path.
512GB unified
Arm CPUAPI & control
Tensor fabricInference
KV-cacheLong context
WeightsLocal & direct
Inference accelerator
Built for the next token.
Hardware that follows the transformer.
DVC-1 keeps weights in motion, cuts idle cycles, and fuses the ops that dominate modern language models. Primary KPIs: tokens per watt, time to first token, cost per million tokens.
FP4INT4INT8FP8BF16Flash AttentionRoPERMSNormMoEPaged KVSpeculative decodeContinuous batching
Minimum for dense FP8 inference. Stretch goal 4 PF by process node, die area, and power envelope.
Quantized decode and batching first. No silicon reserved for graphics or training.
Power & cooling
Rack-class work. Desk-side power.
350 Wdesign target at full inference
Every watt serves the model.
The compact enclosure uses a vapor chamber, two large low-RPM fans, and front-to-back airflow. An internal high-efficiency PSU absorbs short peaks without raising sustained draw.
Scale-up & scale-out
From 512 GB to 51.2 TB.
One node when enough. A hundred when not.
Each unit holds 512 GB of real local unified memory. Multiple nodes form a distributed model pool over UALink switches and RDMA. Memory is not physically local across the cluster — the runtime shards layers, experts, and KV-cache automatically.
5.12 TBdistributed model memory
Connectivity
Four fast ports. No waste.
blackbox / rear fabric
UAL 1
x4
x4
UAL 2
x4
x4
UAL 3
x4
x4
UAL 4
x4
x4
200/400G
RDMA A
RDMA A
200/400G
RDMA B
RDMA B
10G
MGMT
MGMT
USB-C
Service
Service
Four UALink x4. Switch when the cluster grows.
Each x4 port targets up to 100 GB/s per direction at 200 Gbit/s per lane. Four ports yield a theoretical aggregate of 400 GB/s per direction. Five or more nodes use a switched fabric — not a chain.
Why not eight ports on the desk model?
Eight external ports double SerDes lanes, contact area, I/O power, and cooling. Four ports fit a compact node. A rack SKU can reserve eight.
Open software stack
Ubuntu in. Familiar API out.
A local AI service — not a new proprietary stack.
Standard tooling
Ubuntu LTS ARM64, containerd, Kubernetes support, Prometheus metrics, and an OpenAI-compatible REST and streaming API.
Open model formats
Runtime targets for safetensors, GGUF, and ONNX. Conversion and quantization as reproducible pipelines.
Automatic sharding
Runtime splits layers, experts, tensors, and KV-cache across nodes without the API client knowing the topology.
Llama familyQwenMistral & MixtralDeepSeekGemmaTransformersllama.cpp backendvLLM-style serving
Planned system specification
davici blackbox 512.
Product role
Headless inference node for large language models. No local dev environment, no graphics, no model training.
Form factor
220 × 220 × 105 mm, ~5.1 liters. Target weight under 5 kg. CNC aluminum or die-cast magnesium/aluminum. Finish: deep graphite anodized monolith.
SoC
DVC-1 custom inference SoC. 3 nm or 4 nm target, depending on cost, IP maturity, and advanced packaging availability.
Host CPU
12 Arm Neoverse-class 64-bit cores. Ubuntu, networking, tokenization, scheduling, storage, and management. No x86 CPU.
AI accelerator
Transformer-optimized tensor fabric. At least 2 PFLOPS dense FP8 and 4 POPS INT4 as architecture targets. Support for FP4, INT4, INT8, FP8, and BF16. No raster or graphics pipeline.
Fused operations
Attention, RoPE, RMSNorm, LayerNorm, Softmax, SiLU, GELU, SwiGLU, MoE routing, paged KV-cache, prefix-cache, speculative decoding, and continuous batching.
Unified memory
512 GB LPDDR5X or LPDDR6-class memory. Shared physical address space for CPU and accelerator. Controller-level ECC or equivalent end-to-end protection required.
Memory bandwidth
At least 1.0 TB/s theoretical, at least 0.85 TB/s verified sustained. Stretch target 1.2 TB/s. Measurement on the accelerator’s actual data path.
SRAM
At least 256 MB distributed on-die SRAM as design target. Banked and placed near tensor units for weight tiles, activations, and KV blocks.
Scale-up
4 × UALink 200G x4 ports. 100 GB/s per direction per port, 400 GB/s aggregate per direction before protocol overhead. Native memory semantics, P2P DMA, and atomics.Open standard
Scale-out
2 × 200GbE RDMA standard. 400GbE option when power, connector format, and cooling allow. Separate 10GbE management.
PCIe & CXL
PCIe 6.0 root complex. Enough lanes for two NVMe devices, networking, and service. CXL may be reserved for future I/O but must not be the primary model-memory path.
NVMe standard
5 TB usable. One 7.68 TB enterprise NVMe module configured with high overprovisioning for endurance, cache, and stable performance.
NVMe expansion
Second internal serviceable NVMe bay. Identical module yields 10 TB usable total. M.2 22110 or E1.S selected after thermal and mechanical validation.
Management
BMC, secure boot, hardware root of trust, signed firmware, remote console, power cycling, telemetry, and a separate management NIC. No local display required.
Operating system
Ubuntu LTS ARM64. Minimal headless image, containerd, Kubernetes support, OTA updates, metrics, and role-based administration.
API & formats
OpenAI-compatible REST and streaming API. Targets for safetensors, GGUF, and ONNX. Custom kernel runtime, compiler backend, and collective library required.
Cluster size
1 to 100 nodes. 10 nodes → 5.12 TB distributed model memory. 20 → 10.24 TB. 100 → 51.2 TB. Five or more nodes use a switched fabric.
Power
<35 W idle, 220–300 W typical inference, <350 W sustained full inference, <450 W peak. Internal PSU of at least 550 W with Titanium-class (80 PLUS) efficiency as target.
Cooling & acoustics
Vapor chamber, two large centrifugal or axial fans, front-to-back airflow. No throttling under 72-hour full load at 25 °C ambient. Acoustic target under 32 dBA at typical inference.
Removed
GPU graphics, display controller, HDMI/DisplayPort, media codecs, audio DSP, camera ISP, Wi-Fi, Bluetooth, SD reader, training optimizer, and gradient engine.
Acceptance tests
At least 85% of specified memory bandwidth, at least 85% of UALink line rate per port, 72-hour thermal burn-in, node-failure recovery, signed boot chain, and reproducible inference on representative 8B-, 70B-, and 400B-class models.
Deliverables from ASIC partner
- Architecture model, PPA estimates, and memory bandwidth model.
- Arm, LPDDR, PCIe, UALink, Ethernet, and security IP integration.
- RTL, verification, emulation, DFT, physical design, and tapeout.
- Package, substrate, signal integrity, power integrity, and thermal model.
- Boot firmware, Linux BSP, kernel driver, runtime, and profiling tools.
Deliverables from ODM
- Motherboard, VRM, BMC, NVMe, networking, and cabling.
- Chassis, cooling, PSU, acoustics, and serviceability.
- EVT, DVT, and PVT units with complete test documentation.
- EMC, safety, CE, RoHS, WEEE, and production testing.
- Supply chain, second-source plan, and cost model for 1k, 10k, and 100k units.
Technical basis: UALink 200G defines 200 Gbit/s per lane and scale-up to up to 1,024 accelerators per the UALink Consortium. UALink 2.0 was published in April 2026 and adds in-network compute, chiplet definitions, and manageability per the UALink Consortium press room. PCIe 6.0 x16 delivers up to 256 GB/s aggregate bidirectional bandwidth per PCI-SIG. Arm describes Neoverse as a platform for energy-efficient AI infrastructure and accelerator orchestration per Arm.
Tokens.
Nothing else.
Large open models. Local. Scalable. Efficient. Under your control.